The input stage for an operational amplifier ("op amp") is typically a differential amplifier. Turning to FIG. 1, it illustrates a model for an op amp in which a conventional differential input stage amplifies an input signal voltage V.sub.I to produce a pair of circuit currents I.sub.1 and I.sub.2 whose difference is representative of voltage V.sub.I (as long as .vertline.V.sub.I .vertline. is not too large). Input V.sub.I is supplied differentially to the bases of NPN input transistors Q1 and Q2 whose emitters are coupled together through a control point CP. A constant current source 7 connected between point CP and a source for a low supply voltage V.sub.LL provides a supply current I.sub.T for transistors Q1 and Q2. Their collectors respectively provide currents I.sub.1 and I.sub.2 to a subtracting circuit 8 connected to a source of a high supply voltage V.sub.HH. Circuit 8 generates a signal current I.sub.D substantially equal to K(I.sub.1 -I.sub.2), where K is a proportionally constant.
Understanding the operation of this differential amplifier is facilitated with the assistance of FIG. 2 which shows how current I.sub.D varies with voltage V.sub.I (for the case where K=1). When input V.sub.I is zero, current I.sub.D is also zero since I.sub.1 =I.sub.2 =I.sub.T /2. If V.sub.I is increased, I.sub.1 increases towards I.sub.T as transistor Q1 becomes progressively more conductive. I.sub.2 simultaneously decreases as transistor Q2 becomes progressively less conductive. It turns off when V.sub.I reaches about 80 millivolts. A further increase in V.sub.I does not cause any further amplifier changes. The reverse occurs when V.sub.I is reduced. Transistor Q1 becomes progressively less conductive and turns substantially off when V.sub.I reaches about -80 millivolts.
Current I.sub.D from the differential amplifier is usually provided to a stage that capacitively integrates current I.sub.D to produce an output voltage V.sub.O. The integrating stage is shown in FIG. 1 as a capacitor CO connected across a high-gain inverting amplifier 9. Capacitor CO provides frequency compensation for the two stages to make the combination stable for unity-gain feedback. The value C.sub.O of capacitor CO is approximately gm/2.pi.f.sub.O, where g.sub.m is the transconductance of the differential stage, and f.sub.O is the frequency at which the forward gain of the two stages falls to unity.
The slew rate S is the maximum rate at which voltage V.sub.O changes in response to a large step in voltage V.sub.I. For FIG. 1, the V.sub.O rate of change is limited by the rate at which current I.sub.D charges capacitor CO. Since the maximum value of I.sub.D is I.sub.T, S is approximately I.sub.T /CO. The slew rate can then be expressed as EQU S.apprxeq.2.pi.f.sub.O I.sub.T /g.sub.m ( 1)
Unity-gain frequency f.sub.O is typically about 1 megahertz. S is then about 0.3 volt/microsecond. This is often too low.
One way to increase the slew rate at a given value of f.sub.O is to reduce the transconductance by using emitter degeneration resistors R.sub.E1 and R.sub.E2 shown in dashed lines at the respective emitters of transistors Q1 and Q2 in FIG. 1. The transconductance falls approximately to g.sub.m /(1+g.sub.m R.sub.E), where R.sub.E is the nominal value of resistor R.sub.E1 or R.sub.E2. The slew rate is increased by g.sub.m R.sub.E for which 10 is a representative value. Unfortunately, resistor/transistor mis-matching causes the input offset voltage to increase. It typically degrades by around the same factor that the slew rate improves. This is not acceptable.
W. Hearn describes another technique for improving slew rate in U.S. Pat. No. 3,668,538 in which the small-signal transconductance approximately equals g.sub.m for FIG. 1. The maximum current for charging Hearn's compensating capacitor is increased greatly by providing alternate current paths that become operative when the input voltage is large. Hearn can achieve a slew rate of 30-40 volts/microsecond when f.sub.O is about 1 megahertz. However, resistors along the alternate paths must have high values to achieve this slew rate. The normal resistor mis-matching increases the offset voltage and noise. In addition, the use of lateral transistors of opposite polarity to the input transistors significantly worsens the high-frequency behavior of Hearn's device.
In U.S. Pat. No. 4,002,993, the present inventor discloses a slew-rate enhancement technique in which part of the current from an emitter current source is diverted away from the input transistors when the input voltage is small. A sensing circuit causes the fraction of diverted current to decrease when the input voltage becomes large so as to increase the current available to the input transistors. This increases the slew rate. Although offset voltage is not a problem, the common-mode rejection ratio is limited because the sensing circuit is sensitive to component variations.